simdpp::zip16_hi, zip8_hi, zip4_hi, zip2_hi

From libsimdpp-docs
template<unsigned N, class V1, class V2>

Ret<N, _DETAIL_> zip16_hi( const any_vec8<N,V1>& a,

                           const any_vec8<N,V2>& b );
template<unsigned N, class V1, class V2>

Ret<N, _DETAIL_> zip8_hi( const any_vec16<N,V1>& a,

                          const any_vec16<N,V2>& b );
template<unsigned N, class V1, class V2>

Ret<N, _DETAIL_> zip4_hi( const any_vec32<N,V1>& a,

                          const any_vec32<N,V2>& b );
template<unsigned N, class V1, class V2>

Ret<N, _DETAIL_> zip2_hi( const any_vec64<N,V1>& a,

                          const any_vec64<N,V2>& b );

Interleaves elements from the higher halves of two source vectors. Each 128-bit lane within vectors is processed separately.

The return vector type is governed by the expression promotion rules.

Parameters[edit]

a, b - source vectors

Return value[edit]

A vector expression.

Equivalent operation[edit]

For the uint32x4 case:

r = [ a2 b2 a3 b3 ]

For the uint32x8 case:

r = [ a2 b2 a3 b3 a6 b6 a7 b7 ]

See also[edit]