libsimdpp  0.9.3
Functions
Operations: shift

Functions

int8x16 simdpp::shift_r (int8x16 a, unsigned count)
 Shifts signed 8-bit values right by count bits while shifting in the sign bit. More...
 
int8x32 simdpp::shift_r (int8x32 a, unsigned count)
 
uint8x16 simdpp::shift_r (uint8x16 a, unsigned count)
 Shifts unsigned 8-bit values right by count bits while shifting in zeros. More...
 
uint8x32 simdpp::shift_r (uint8x32 a, unsigned count)
 Shifts unsigned 8-bit values right by count bits while shifting in zeros. More...
 
int16x8 simdpp::shift_r (int16x8 a, unsigned count)
 Shifts signed 16-bit values right by count bits while shifting in the sign bit. More...
 
int16x16 simdpp::shift_r (int16x16 a, unsigned count)
 Shifts signed 16-bit values right by count bits while shifting in the sign bit. More...
 
uint16x8 simdpp::shift_r (uint16x8 a, unsigned count)
 Shifts unsigned 16-bit values right by count bits while shifting in zeros. More...
 
uint16x16 simdpp::shift_r (uint16x16 a, unsigned count)
 Shifts unsigned 16-bit values right by count bits while shifting in zeros. More...
 
int32x4 simdpp::shift_r (int32x4 a, unsigned count)
 Shifts signed 32-bit values right by count bits while shifting in the sign bit. More...
 
int32x8 simdpp::shift_r (int32x8 a, unsigned count)
 Shifts signed 32-bit values right by count bits while shifting in the sign bit. More...
 
uint32x4 simdpp::shift_r (uint32x4 a, unsigned count)
 Shifts unsigned 32-bit values right by count bits while shifting in zeros. More...
 
uint32x8 simdpp::shift_r (uint32x8 a, unsigned count)
 Shifts unsigned 32-bit values right by count bits while shifting in zeros. More...
 
int64x2 simdpp::shift_r (int64x2 a, unsigned count)
 Shifts signed 64-bit values right by count bits while shifting in the sign bit. More...
 
int64x4 simdpp::shift_r (int64x4 a, unsigned count)
 Shifts signed 64-bit values right by count bits while shifting in the sign bit. More...
 
uint64x2 simdpp::shift_r (uint64x2 a, unsigned count)
 Shifts unsigned 64-bit values right by count bits while shifting in zeros. More...
 
uint64x4 simdpp::shift_r (uint64x4 a, unsigned count)
 Shifts unsigned 64-bit values right by count bits while shifting in zeros. More...
 
basic_int8x16 simdpp::shift_l (basic_int8x16 a, unsigned count)
 Shifts 8-bit values left by count bits while shifting in zeros. More...
 
basic_int8x32 simdpp::shift_l (basic_int8x32 a, unsigned count)
 Shifts 8-bit values left by count bits while shifting in zeros. More...
 
basic_int16x8 simdpp::shift_l (basic_int16x8 a, unsigned count)
 Shifts 16-bit values left by count bits while shifting in zeros. More...
 
basic_int16x16 simdpp::shift_l (basic_int16x16 a, unsigned count)
 Shifts 16-bit values left by count bits while shifting in zeros. More...
 
basic_int32x4 simdpp::shift_l (basic_int32x4 a, unsigned count)
 Shifts 32-bit values left by count bits while shifting in zeros. More...
 
basic_int32x8 simdpp::shift_l (basic_int32x8 a, unsigned count)
 Shifts 32-bit values left by count bits while shifting in zeros. More...
 
basic_int64x2 simdpp::shift_l (basic_int64x2 a, unsigned count)
 Shifts 64-bit values left by count bits while shifting in zeros. More...
 
basic_int64x4 simdpp::shift_l (basic_int64x4 a, unsigned count)
 Shifts 64-bit values left by count bits while shifting in zeros. More...
 
template<unsigned count>
int8x16 simdpp::shift_r (int8x16 a)
 Shifts signed 8-bit values right by count bits while shifting in the sign bit. More...
 
template<unsigned count>
int8x32 simdpp::shift_r (int8x32 a)
 Shifts signed 8-bit values right by count bits while shifting in the sign bit. More...
 
template<unsigned count>
uint8x16 simdpp::shift_r (uint8x16 a)
 Shifts unsigned 8-bit values right by count bits while shifting in zeros. More...
 
template<unsigned count>
uint8x32 simdpp::shift_r (uint8x32 a)
 Shifts unsigned 8-bit values right by count bits while shifting in zeros. More...
 
template<unsigned count>
int16x8 simdpp::shift_r (int16x8 a)
 Shifts signed 16-bit values right by count bits while shifting in the sign bit. More...
 
template<unsigned count>
int16x16 simdpp::shift_r (int16x16 a)
 Shifts signed 16-bit values right by count bits while shifting in the sign bit. More...
 
template<unsigned count>
uint16x8 simdpp::shift_r (uint16x8 a)
 Shifts unsigned 16-bit values right by count bits while shifting in zeros. More...
 
template<unsigned count>
uint16x16 simdpp::shift_r (uint16x16 a)
 Shifts unsigned 16-bit values right by count bits while shifting in zeros. More...
 
template<unsigned count>
int32x4 simdpp::shift_r (int32x4 a)
 Shifts signed 32-bit values right by count bits while shifting in the sign bit. More...
 
template<unsigned count>
int32x8 simdpp::shift_r (int32x8 a)
 Shifts signed 32-bit values right by count bits while shifting in the sign bit. More...
 
template<unsigned count>
uint32x4 simdpp::shift_r (uint32x4 a)
 Shifts unsigned 32-bit values right by count bits while shifting in zeros. More...
 
template<unsigned count>
uint32x8 simdpp::shift_r (uint32x8 a)
 Shifts unsigned 32-bit values right by count bits while shifting in zeros. More...
 
template<unsigned count>
int64x2 simdpp::shift_r (int64x2 a)
 Shifts signed 64-bit values right by count bits while shifting in the sign bit. More...
 
template<unsigned count>
int64x4 simdpp::shift_r (int64x4 a)
 Shifts signed 64-bit values right by count bits while shifting in the sign bit. More...
 
template<unsigned count>
uint64x2 simdpp::shift_r (uint64x2 a)
 Shifts unsigned 64-bit values right by count bits while shifting in zeros. More...
 
template<unsigned count>
uint64x4 simdpp::shift_r (uint64x4 a)
 Shifts unsigned 64-bit values right by count bits while shifting in zeros. More...
 
template<unsigned count>
basic_int8x16 simdpp::shift_l (basic_int8x16 a)
 Shifts 8-bit values left by count bits while shifting in zeros. More...
 
template<unsigned count>
basic_int8x32 simdpp::shift_l (basic_int8x32 a)
 Shifts 8-bit values left by count bits while shifting in zeros. More...
 
template<unsigned count>
basic_int16x8 simdpp::shift_l (basic_int16x8 a)
 Shifts 16-bit values left by count bits while shifting in zeros. More...
 
template<unsigned count>
basic_int16x16 simdpp::shift_l (basic_int16x16 a)
 Shifts 16-bit values left by count bits while shifting in zeros. More...
 
template<unsigned count>
basic_int32x4 simdpp::shift_l (basic_int32x4 a)
 Shifts 32-bit values left by count bits while shifting in zeros. More...
 
template<unsigned count>
basic_int32x8 simdpp::shift_l (basic_int32x8 a)
 Shifts 32-bit values left by count bits while shifting in zeros. More...
 
template<unsigned count>
basic_int64x2 simdpp::shift_l (basic_int64x2 a)
 Shifts 64-bit values left by count bits while shifting in zeros. More...
 
template<unsigned count>
basic_int64x4 simdpp::shift_l (basic_int64x4 a)
 Shifts 64-bit values left by count bits while shifting in zeros. More...
 

Detailed Description

Function Documentation

basic_int8x16 simdpp::shift_l ( basic_int8x16  a,
unsigned  count 
)
inline

Shifts 8-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In SSE2-AVX this intrinsic results in at least 4-5 instructions.
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 8-9 instructions.
  • In AVX2 this intrinsic results in at least 4-5 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
basic_int8x32 simdpp::shift_l ( basic_int8x32  a,
unsigned  count 
)
inline

Shifts 8-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In SSE2-AVX this intrinsic results in at least 4-5 instructions.
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 8-9 instructions.
  • In AVX2 this intrinsic results in at least 4-5 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
basic_int16x8 simdpp::shift_l ( basic_int16x8  a,
unsigned  count 
)
inline

Shifts 16-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
basic_int16x16 simdpp::shift_l ( basic_int16x16  a,
unsigned  count 
)
inline

Shifts 16-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
basic_int32x4 simdpp::shift_l ( basic_int32x4  a,
unsigned  count 
)
inline

Shifts 32-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
basic_int32x8 simdpp::shift_l ( basic_int32x8  a,
unsigned  count 
)
inline

Shifts 32-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
basic_int64x2 simdpp::shift_l ( basic_int64x2  a,
unsigned  count 
)
inline

Shifts 64-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • Not implemented for ALTIVEC.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • Not implemented for ALTIVEC.
basic_int64x4 simdpp::shift_l ( basic_int64x4  a,
unsigned  count 
)
inline

Shifts 64-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • Not implemented for ALTIVEC.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • Not implemented for ALTIVEC.
template<unsigned count>
basic_int8x16 simdpp::shift_l ( basic_int8x16  a)

Shifts 8-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In SSE2-AVX2 this intrinsic results in at least 2-3 instructions.
  • In NEON this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 4-5 instructions.
  • In AVX2 and NEON this intrinsic results in at least 2-3 instructions.
template<unsigned count>
basic_int8x32 simdpp::shift_l ( basic_int8x32  a)
inline

Shifts 8-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In SSE2-AVX2 this intrinsic results in at least 2-3 instructions.
  • In NEON this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 4-5 instructions.
  • In AVX2 and NEON this intrinsic results in at least 2-3 instructions.
template<unsigned count>
basic_int16x8 simdpp::shift_l ( basic_int16x8  a)

Shifts 16-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
basic_int16x16 simdpp::shift_l ( basic_int16x16  a)
inline

Shifts 16-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
basic_int32x4 simdpp::shift_l ( basic_int32x4  a)

Shifts 32-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
basic_int32x8 simdpp::shift_l ( basic_int32x8  a)
inline

Shifts 32-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
basic_int64x2 simdpp::shift_l ( basic_int64x2  a)

Shifts 64-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
  • Not implemented for ALTIVEC.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • Not implemented for ALTIVEC.
template<unsigned count>
basic_int64x4 simdpp::shift_l ( basic_int64x4  a)
inline

Shifts 64-bit values left by count bits while shifting in zeros.

r0 = a0 << count
...
rN = aN << count
  • Not implemented for ALTIVEC.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • Not implemented for ALTIVEC.
int8x16 simdpp::shift_r ( int8x16  a,
unsigned  count 
)
inline

Shifts signed 8-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In SSE2-AVX2 this intrinsic results in at least 6 instructions.
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 12 instructions.
  • In AVX2 this intrinsic results in at least 6 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
int8x32 simdpp::shift_r ( int8x32  a,
unsigned  count 
)
inline
uint8x16 simdpp::shift_r ( uint8x16  a,
unsigned  count 
)
inline

Shifts unsigned 8-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In SSE2-AVX2 this intrinsic results in at least 4-5 instructions.
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 8-9 instructions.
  • In AVX2 this intrinsic results in at least 4-5 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
uint8x32 simdpp::shift_r ( uint8x32  a,
unsigned  count 
)
inline

Shifts unsigned 8-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In SSE2-AVX2 this intrinsic results in at least 4-5 instructions.
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 8-9 instructions.
  • In AVX2 this intrinsic results in at least 4-5 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
int16x8 simdpp::shift_r ( int16x8  a,
unsigned  count 
)
inline

Shifts signed 16-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
int16x16 simdpp::shift_r ( int16x16  a,
unsigned  count 
)
inline

Shifts signed 16-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
uint16x8 simdpp::shift_r ( uint16x8  a,
unsigned  count 
)
inline

Shifts unsigned 16-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
uint16x16 simdpp::shift_r ( uint16x16  a,
unsigned  count 
)
inline

Shifts unsigned 16-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
int32x4 simdpp::shift_r ( int32x4  a,
unsigned  count 
)
inline

Shifts signed 32-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
r0 = a0 >> count
...
rN = aN >> count
  • In NEON this intrinsic results in at least 2 instructions.
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
int32x8 simdpp::shift_r ( int32x8  a,
unsigned  count 
)
inline

Shifts signed 32-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
r0 = a0 >> count
...
rN = aN >> count
  • In NEON this intrinsic results in at least 2 instructions.
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
uint32x4 simdpp::shift_r ( uint32x4  a,
unsigned  count 
)
inline

Shifts unsigned 32-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
uint32x8 simdpp::shift_r ( uint32x8  a,
unsigned  count 
)
inline

Shifts unsigned 32-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • In ALTIVEC this intrinsic results in at least 1-4 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • In ALTIVEC this intrinsic results in at least 2-5 instructions.
int64x2 simdpp::shift_r ( int64x2  a,
unsigned  count 
)
inline

Shifts signed 64-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In SSE2-AVX2 this intrinsic results in at least 4-6 instructions.
  • In NEON this intrinsic results in at least 2 instructions.
  • Not implemented for ALTIVEC.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 8-10 instructions.
  • In AVX2 this intrinsic results in at least 4-6 instructions.
  • In NEON this intrinsic results in at least 3 instructions.
  • Not implemented for ALTIVEC.
int64x4 simdpp::shift_r ( int64x4  a,
unsigned  count 
)
inline

Shifts signed 64-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In SSE2-AVX2 this intrinsic results in at least 4-6 instructions.
  • In NEON this intrinsic results in at least 2 instructions.
  • Not implemented for ALTIVEC.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 8-10 instructions.
  • In AVX2 this intrinsic results in at least 4-6 instructions.
  • In NEON this intrinsic results in at least 3 instructions.
  • Not implemented for ALTIVEC.
uint64x2 simdpp::shift_r ( uint64x2  a,
unsigned  count 
)
inline

Shifts unsigned 64-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • Not implemented for ALTIVEC.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • Not implemented for ALTIVEC.
uint64x4 simdpp::shift_r ( uint64x4  a,
unsigned  count 
)
inline

Shifts unsigned 64-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In NEON this intrinsic results in at least 1-2 instructions.
  • Not implemented for ALTIVEC.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 2 instructions.
  • In NEON this intrinsic results in at least 2-3 instructions.
  • Not implemented for ALTIVEC.
template<unsigned count>
int8x16 simdpp::shift_r ( int8x16  a)

Shifts signed 8-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In SSE2-AVX2 this intrinsic results in at least 6 instructions.
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 12 instructions.
  • In AVX2 this intrinsic results in at least 6 instructions.
  • In NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
int8x32 simdpp::shift_r ( int8x32  a)

Shifts signed 8-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In SSE2-AVX2 this intrinsic results in at least 6 instructions.
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 12 instructions.
  • In AVX2 this intrinsic results in at least 6 instructions.
  • In NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
uint8x16 simdpp::shift_r ( uint8x16  a)

Shifts unsigned 8-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
  • In SSE2-AVX2 this intrinsic results in at least 2-3 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 4-5 instructions.
  • In AVX2 this intrinsic results in at least 2-3 instructions.
  • In NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
uint8x32 simdpp::shift_r ( uint8x32  a)

Shifts unsigned 8-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
  • In SSE2-AVX2 this intrinsic results in at least 2-3 instructions.
256-bit version:
  • In SSE2-AVX this intrinsic results in at least 4-5 instructions.
  • In AVX2 this intrinsic results in at least 2-3 instructions.
  • In NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
int16x8 simdpp::shift_r ( int16x8  a)

Shifts signed 16-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
int16x16 simdpp::shift_r ( int16x16  a)

Shifts signed 16-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
uint16x8 simdpp::shift_r ( uint16x8  a)

Shifts unsigned 16-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
uint16x16 simdpp::shift_r ( uint16x16  a)

Shifts unsigned 16-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
int32x4 simdpp::shift_r ( int32x4  a)

Shifts signed 32-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
int32x8 simdpp::shift_r ( int32x8  a)

Shifts signed 32-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
uint32x4 simdpp::shift_r ( uint32x4  a)

Shifts unsigned 32-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
uint32x8 simdpp::shift_r ( uint32x8  a)

Shifts unsigned 32-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • In ALTIVEC this intrinsic results in at least 1-2 instructions.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • In ALTIVEC this intrinsic results in at least 2-3 instructions.
template<unsigned count>
int64x2 simdpp::shift_r ( int64x2  a)

Shifts signed 64-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • Not vectorized in SSE2-AVX2.
  • In SSE2-AVX2 this intrinsic results in at least 4-6 instructions.
  • Not implemented for ALTIVEC.
256-bit version:
  • Not vectorized in SSE2-AVX.
  • In SSE2-AVX this intrinsic results in at least 8-10 instructions.
  • In AVX2 this intrinsic results in at least 4-6 instructions.
  • In NEON this intrinsic results in at least 2 instructions.
  • Not implemented for ALTIVEC.
template<unsigned count>
int64x4 simdpp::shift_r ( int64x4  a)

Shifts signed 64-bit values right by count bits while shifting in the sign bit.

r0 = a0 >> count
...
rN = aN >> count
128-bit version:
  • Not vectorized in SSE2-AVX2.
  • In SSE2-AVX2 this intrinsic results in at least 4-6 instructions.
  • Not implemented for ALTIVEC.
256-bit version:
  • Not vectorized in SSE2-AVX.
  • In SSE2-AVX this intrinsic results in at least 8-10 instructions.
  • In AVX2 this intrinsic results in at least 4-6 instructions.
  • In NEON this intrinsic results in at least 2 instructions.
  • Not implemented for ALTIVEC.
template<unsigned count>
uint64x2 simdpp::shift_r ( uint64x2  a)

Shifts unsigned 64-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
  • Not implemented for ALTIVEC.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • Not implemented for ALTIVEC.
template<unsigned count>
uint64x4 simdpp::shift_r ( uint64x4  a)

Shifts unsigned 64-bit values right by count bits while shifting in zeros.

r0 = a0 >> count
...
rN = aN >> count
  • Not implemented for ALTIVEC.
256-bit version:
  • In SSE2-AVX and NEON this intrinsic results in at least 2 instructions.
  • Not implemented for ALTIVEC.
Generated on Thu Oct 31 2013 04:08:51 for libsimdpp by   doxygen 1.8.3.1